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Title:
LOAD SIMULATION METHOD OF PROCESSOR
Document Type and Number:
Japanese Patent JPS59168553
Kind Code:
A
Abstract:

PURPOSE: To perform the load simulation of a main processor by providing the main processor with a function which stores the telegrams transferred between the main processor and a terminal device after dividing them for every desired quantity, and a memory region which stores the divided telegrams, then making use of these telegrams.

CONSTITUTION: The data given from a terminal device group 1 are supplied to a main processor 4 via a secondary processor 2 and a communication circuit 3. The processor 4 transfers the data of a file 5 with the group 1. Then the processor 4 extracts the input data through an extracting circuit 6 and edits the extracted data through a processing part 7 to produce the ascending telegrams. These telegrams are stored to a magnetic tape 8 in the order of input. If an increase is planned to the group 1, it is required to check whether the processor 4 can cope with the increased load. In this case, the tape device 8 storing said ascending telegrams is used. Then the processor 2 sends the ascending telegrams to the processor 4.


Inventors:
SAKAE HISAO
Application Number:
JP4489083A
Publication Date:
September 22, 1984
Filing Date:
March 16, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/22; G06F11/26; (IPC1-7): G06F11/26
Attorney, Agent or Firm:
Koshiro Matsuoka



 
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