Title:
Local clear control
Document Type and Number:
Japanese Patent JP6284130
Kind Code:
B2
Abstract:
A computer implemented instruction is executed. One or more translation table entry locations (TLB) are specified by the instruction. Based on a local-clearing (LC) control specified by the instruction being a first value, the processor selectively clears TLBs in a plurality of the CPUs in a configuration of entries corresponding to the determined translation table entry location. Based on the local-clearing (LC) being a second value, the processor selectively clears only the TLBs of the CPU executing the instruction of entries corresponding to the determined translation table entry location. A computer program product, computer system and computer implemented method are provided.
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Inventors:
Greiner, Dan
Jitman, Gustav
Jitman, Gustav
Application Number:
JP2015516532A
Publication Date:
February 28, 2018
Filing Date:
May 21, 2013
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
G06F12/10; G06F12/12
Domestic Patent References:
| JP61248135A | ||||
| JP2006526203A | ||||
| JP63201854A |
Foreign References:
| US20050027960 | ||||
| US20040230749 | ||||
| US20110040950 | ||||
| US20110119466 | ||||
| US20040064618 |
Other References:
中森 章,初めて読むMIPS 第2回,Oh!X 2000春号,2000年 4月 9日,pp.227-228
インテル株式会社,インテル・アーキテクチャ・ソフトウェア・ディベロッパーズ・マニュアル 中巻:命令セット・リファレンス,1997年,第1版,p.3-232
インテル株式会社,インテル・アーキテクチャ・ソフトウェア・ディベロッパーズ・マニュアル 中巻:命令セット・リファレンス,1997年,第1版,p.3-232
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Tasaichi Tanae