Title:
LOCAL OSCILLATION CIRCUIT AND HETERODYNE RECEIVER USING THE SAME
Document Type and Number:
Japanese Patent JP2016122890
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a local oscillation circuit which is to be used in a super-heterodyne receiver and is capable of achieving low cost in reducing phase noise using a direct digital synthesizer (DDS).SOLUTION: As a clock input to a DDS 2, a signal is used that is obtained by converting an oscillation signal of a temperature compensation type voltage control crystal oscillator (OCXO) 7 into a high frequency using two-stage phase-locked oscillators (PLO) 10, 20. By using a high clock frequency in the DDS 2, phase noise is significantly reduced proportionately with its division ratio. An oscillation frequency of the OCXO 7 is lowered by the DDS 2 with a high clock frequency, thus achieving low cost of a local oscillation circuit 1.SELECTED DRAWING: Figure 1
More Like This:
| JP2006180165 | PLL SYNTHESIZER AND MULTIBAND WIRELESS EQUIPMENT USING THE SAME |
| JP2825045 | [Title of Invention] Frequency Synthesizer |
| JP2003258633 | PLL MODULE |
Inventors:
NAGASHIMA SHIGEKI
Application Number:
JP2014260449A
Publication Date:
July 07, 2016
Filing Date:
December 24, 2014
Export Citation:
Assignee:
ICOM INC
International Classes:
H03L7/18; H03L7/08; H03L7/093; H04B1/26
Domestic Patent References:
| JPH066179A | 1994-01-14 | |||
| JP2009296341A | 2009-12-17 | |||
| JP2010500830A | 2010-01-07 | |||
| JPS6059822A | 1985-04-06 | |||
| JP2002271192A | 2002-09-20 | |||
| JP2008099097A | 2008-04-24 | |||
| JP2006310940A | 2006-11-09 | |||
| JP2000261318A | 2000-09-22 | |||
| JP2005519517A | 2005-06-30 |
Foreign References:
| US20050266818A1 | 2005-12-01 | |||
| US20110080528A1 | 2011-04-07 |
Attorney, Agent or Firm:
Katsunori Sugimoto
Mitsuhiro Okada
Mitsuhiro Okada
Previous Patent: IMAGE FORMATION APPARATUS
Next Patent: RADIO COMMUNICATION SYSTEM AND RELAY COMMUNICATION BUOY
Next Patent: RADIO COMMUNICATION SYSTEM AND RELAY COMMUNICATION BUOY