PURPOSE: To obtain a lock detection signal securely by providing a filter function circuit which inputs the pulse output of a phase comparing circuit and a counter function circuit which inputs the output of the filter function circuit.

CONSTITUTION: When there is a phase difference in falling between pulses of a reference signal (8e) and a comparison signal (f), a phase difference output signal (g) is an L-level pulse corresponding to the phase difference. This signal (g) passes through a filter circuit 22 to generate a filter output signal (h), which resets a counter circuit 23 while a lock signal (i) is at a level L. The circuit 23 generates an H-level clock output signal (i) by comparison by a phase comparing circuit 21 at every fall of the signal (e) only when the phase difference becomes small enough not to pass the signal through the circuit 22 or when there is no position difference in specific time t3 from the ceasing of the phase difference signal, thereby detecting a clock state.