Title:
DATA PROCESSOR
Document Type and Number:
Japanese Patent JP3214831
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a data processor capable of obtaining an arithmetic result by a fast product-sum operation and being made, small in size and low in cast.
SOLUTION: Picture element data f0-f7 are inputted to shift registers one bit by one and they are outputted while they are shifted. The same digits of picture data f0-f3 outputted from the four shift registers are given to operation tables 61a-68a as addresses. The same digits of picture element data f4-f7 outputted from the other four shift registers one by one bit are given to operation tables 61b-68b as the addresses. Calculation results outputted from the operation tables 61a, 61b-68a and 68b are given to adders 71-78 and addition results outputted from adders 71-78 are given to one of input terminals of adders 81-88. Data outputted from the adders 81-88 are given to the other input terminals of the adders 81-88 through registers 91-98.
Inventors:
Kenji Hirano
Shinji Kitamura
Shinji Kitamura
Application Number:
JP6315698A
Publication Date:
October 02, 2001
Filing Date:
March 13, 1998
Export Citation:
Assignee:
Kanebo Co., Ltd.
International Classes:
H04N1/41; G06F17/10; G06F17/14; G06T1/00; G06T1/20; H04N19/423; H04N19/426; H04N19/60; H04N19/625; H04N19/91; (IPC1-7): G06F17/10; G06F17/14
Domestic Patent References:
| JP5153402A | ||||
| JP7152730A | ||||
| JP453362A | ||||
| JP6274524A | ||||
| JP5932061A | ||||
| JP7262175A | ||||
| JP7306849A |
Attorney, Agent or Firm:
Yoshito Fukushima