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Title:
Log Likelihood Ratio (LLR) Attenuation in Low Density Parity Check (LDPC) Decoder
Document Type and Number:
Japanese Patent JP6367607
Kind Code:
B2
Abstract:
Described embodiments provide a media controller to read data stored in a media. The media controller determines a value for each bit of a shortened codeword from the media. The shortened LDPC codeword includes a plurality of non-shortened bits of a full codeword, where the full codeword includes the plurality of non-shortened bits and one or more shortened bits. Shortened bits correspond to bits unused in the shortened codeword. The media controller converts the determined values for each bit of the shortened codeword into a first set of log-likelihood ratio (LLR) values. The full codeword is decoded using the first set of LLR values for the shortened codeword. If the LDPC decoding fails, the media controller dampens one or more LLR values corresponding to non-shortened bits of the codeword to produce a second set of LLR values and starts a second LDPC decoding trial using the second set of LLR values. The dampening of LLR values includes scaling by a predetermined scaling factor and decreasing their magnitude by a predetermined amount.

Inventors:
RT Tea Cohen
Erich F. Harach
Abdel-Hakim S. Alfsein
Application Number:
JP2014103075A
Publication Date:
August 01, 2018
Filing Date:
May 19, 2014
Export Citation:
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Assignee:
LSI LOGIC CORPORATION
International Classes:
H03M13/45; G11B20/10; G11B20/18; G11C16/06; H03M13/19
Foreign References:
US20120272000
WO2011036864A1
Other References:
Yu Cai et al.,Flash Correct-and-Refresh: Retention - Aware Error Management for Increased Flash Memory Lifetime,Computer Design(ICCD), 2012 IEEE 30th International Conference on,2012年10月 3日,pp.94-101
Attorney, Agent or Firm:
Satoshi Furuya
Akihiro Onishi
Kiyoharu Nishiyama
Rei Hosoi