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Patent Searching and Data


Title:
LOGARITHM TRANSFORMER
Document Type and Number:
Japanese Patent JPH02234282
Kind Code:
A
Abstract:

PURPOSE: To attain a logarithm transformation with excellent liniarity as a whole by offsetting the increment/decrement of the output level of a logarithm circuit caused by passing an external input signal through a variable gain circuit.

CONSTITUTION: The level of an external input signal Vin is decided by a level deciding circuit 9, and the external input signal is inputted through a variable gain circuit 5, whose gain is changed according to a decision output, to a logarithm circuit 6, and a corrected voltage, which is changed according to the gain of the variable gain circuit 5, is outputted from a corrected voltage generating circuit 7. By subtracting or adding the corrected voltage from/to the output signal of the logarithm circuit 6, an external output signal is obtained. Consequently the increment/decrement of the output level of the logarithm circuit 6 caused by passing the external input signal Vin through the variable gain circuit 5 is offset. Thus the logarithm transformation at the excellent linearity is attained as a whole.


Inventors:
SUGIYAMA KATSUYASU
Application Number:
JP5546689A
Publication Date:
September 17, 1990
Filing Date:
March 08, 1989
Export Citation:
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Assignee:
MATSUSHITA GRAPHIC COMMUNIC
International Classes:
H04N1/407; G06T5/00; H04N1/40; (IPC1-7): G06F15/68; H04N1/40
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)