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Title:
LOGARITHMIC/ANTI-LOGARITHMIC CONVERTER CIRCUIT
Document Type and Number:
Japanese Patent JP2013096851
Kind Code:
A
Abstract:

To provide a logarithmic/anti-logarithmic converter circuit in which an output signal obtained when performing anti-logarithmic conversion can retain linearity without executing a temperature correction.

The logarithmic/anti-logarithmic converter circuit is so configured that a current signal Iin passing through a current feedback transistor TR 2 of a logarithmic conversion circuit 1 is input in an anti-logarithmic converter circuit 2, a current/voltage converter circuit 3 convers the current signal Iin into a voltage value corresponding thereto, and a subtraction circuit 4 outputs a difference between the output voltage of the current/voltage converter circuit 3 and a preset reference voltage. The subtraction circuit 4 is configured to set a circuit constant such that the difference output has the linearity proportional to the current signal Iin.


Inventors:
NAKAI TOSHIMITSU
Application Number:
JP2011240182A
Publication Date:
May 20, 2013
Filing Date:
November 01, 2011
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G01D3/02; G01R15/00; H03F1/30; H03F3/34
Attorney, Agent or Firm:
Keigo Murakami
Masuo Oiwa
Kenji Yoshizawa
Takenaka Ikuo