PURPOSE: To provide a logic circuit design device which generates a total truth table logically equivalent to sets of partial truth tables (including sets of Boolean expressions) from these sets of partial truth tables to design a logic circuit.
CONSTITUTION: At least one set of sets of partial truth tables where external input/output variables indicating the external input/output terminals of a function block are taken as input/output variables, sets of partial truth tables where intermediate variables indicating the internal signal lines of the function block are included in input/output variables, and sets of Boolean expressions where external input/output variables or intermediate variables are taken as input/ output variables is inputted, and sets of Boolean expressions are converts to sets of partial truth tables of one output variable, and sets of partial truth tables including intermediate variables in input/output variables are converted to sets of partial truth tables where external, input/output variables are taken as input/output variables, and the total truth table is generated from these converted sets and sets of partial truth tables where external input/output variables are taken as input/output variables, and the logic circuit is generated in accordance with the obtained total truth table.
| WO/2009/158466 | SYSTEM AND METHOD FOR COLLISION-FREE CAD DESIGN OF PIPE AND TUBE PATHS |
| WO/2006/094769 | METHOD FOR DESIGNING AN INTEGRATED CIRCUIT |
| JPH02132561 | AUTOMATIC WIRING SYSTEM |
SHIMA KAZUMASA
MATSUMOTO KAZUHIKO
NIIYA TAKAO
KOJIMA SATOSHI
WATAI HIROO
HIKOSAKA MICHIHIRO
KUWABARA NOBUHIRO
HITACHI MICOM SYST KK
Next Patent: METHOD AND DEVICE FOR DECIDING CONFIGURATION OF INTEGRATED CIRCUIT