Title:
LOGIC CIRCUIT AND DESIGN FOR TESTABILITY EMPLOYING IT
Document Type and Number:
Japanese Patent JP3474214
Kind Code:
B2
Abstract:
PURPOSE: To provide a logic circuit in which functions similar to those of BIL BO are realized without inserting any AND circuit into a data path connecting a circuit to be tested and an LFSR, and a design for testability employing the logic circuit.
CONSTITUTION: The logic circuit comprises a first circuit 4 outputting a second input signal and inverted value thereof according to a first control signal, a second circuit 5 outputting the second input signal or the inverted value thereof selectively according to a first input signal and then inverting the selected signal to produce exclusive NOR value of the first and second input signals, and a third circuit 6 delivering a third input signal or a fixed value, as the second input signal, to the first circuit according to a third control signal.
More Like This:
| WO/2003/093844 | SECURE SCAN |
| JPH09166646 | SEMICONDUCTOR DEVICE |
Inventors:
Yasuyuki Nozuyama
Application Number:
JP28410192A
Publication Date:
December 08, 2003
Filing Date:
October 22, 1992
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G01R31/3185; G01R31/28; H03K17/693; H03K19/21; (IPC1-7): G01R31/28
Domestic Patent References:
| JP4140677A | ||||
| JP469580A | ||||
| JP3118641A | ||||
| JP4255000A |
Attorney, Agent or Firm:
Hidekazu Miyoshi
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