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Patent Searching and Data


Title:
LOGIC CIRCUIT FUNCTIONAL VERIFICATION METHOD
Document Type and Number:
Japanese Patent JP2006268481
Kind Code:
A
Abstract:

To increase efficiency and improve quality in testing a logic circuit by software program and also facilitate development of software and hardware in cooperation.

Verification of a logic circuit including software (henceforth called as device software) for controlling a logic circuit block is constituted to have; a process which specifies a plurality of pieces of device software and obtains functions in these programs; a process which calls these functions at random and executes them; a process which acquires arguments acquired from the device software which controls the block in the logic circuit to be a verification object and passed to a called function; and a process which creates a device soft function database constituted by information of the function and the arguments acquired in above processes.


Inventors:
SONO SHIZUKA
Application Number:
JP2005086168A
Publication Date:
October 05, 2006
Filing Date:
March 24, 2005
Export Citation:
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Assignee:
CANON KK
International Classes:
G06F11/22; G06F17/50; H03K19/00
Attorney, Agent or Firm:
Keizo Nishiyama
Yuichi Uchio