LOGIC CIRCUIT AND ITS TESTING METHOD

Title:

LOGIC CIRCUIT AND ITS TESTING METHOD

Document Type and Number:

Japanese Patent JP2713123

Kind Code:

B2

Abstract:

PURPOSE: To eliminate the need of any terminal required for setting a test mode by setting the test mode when it is detected that a prescribed pattern is sent to a test signal.
CONSTITUTION: A logic circuit 1 has a mode switching section 2 and logic section 3. The section 2 sets a mode instructing signal 54 at '1' when the section 2 detects that a test mode setting pattern is sent to a test signal 51 and at '0' when the section 2 detects that a test mode canceling pattern is sent to the signal 51. A tester 4 executes tests on the circuit 1 by sending the test signal 51 composed of the test mode setting pattern, a test pattern, and test mode canceling pattern to the circuit 1.

Inventors:

Naoki Kobayashi

Application Number:

JP29498193A

Publication Date:

February 16, 1998

Filing Date:

November 25, 1993

Export Citation:

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