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Title:
LOGIC CIRCUIT FOR MULTIPLIER
Document Type and Number:
Japanese Patent JPS6453228
Kind Code:
A
Abstract:

PURPOSE: To realize multiplication with optional accuracy and without using any complicated circuit for rounding, by supplying the rounding signal produced with an optional bit to a multiplication/addition unit circuit set at the preceding stage so that a rounding is carried out with an optional bit.

CONSTITUTION: The rounding addition is carried out in the same way as the production of a partial product when '1' of the rounding signal is added to a sum input terminal 34 led from the preceding stage of the multiplication/ addition unit circuits B23, 26 and 29 set at the preceding stage where the multiplicand data is inputted. The rounding signal is produced by the bit selected by a round signal generating circuit 45 after the rounding control signals are received from the rounding control input terminals 43 and 44. As a result, the rounding position can be optionally changed by the rounding control signal and therefore the number of valid bits of the desired result of multiplication is also changed optionally.


Inventors:
YOSHIDA TOSHIHIRO
Application Number:
JP20834787A
Publication Date:
March 01, 1989
Filing Date:
August 24, 1987
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F7/53; G06F7/38; G06F7/483; G06F7/508; G06F7/52; (IPC1-7): G06F7/38; G06F7/52
Domestic Patent References:
JPS62120535A1987-06-01
JPS6222146A1987-01-30
Attorney, Agent or Firm:
Hiroaki Tazawa