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Title:
LOGIC CIRCUIT TESTING SYSTEM
Document Type and Number:
Japanese Patent JPH0560833
Kind Code:
A
Abstract:

PURPOSE: To generate the necessary minimum number of test patterns so as to efficiently test a new logic circuit by extracting a changing extent by comparing an old logic circuit with the new logic circuit and limiting an influenced part, and then, deciding a retesting extent by limiting an influencing part corresponding to the influenced part.

CONSTITUTION: An inverter 17 is obtained by comparing a new logic circuit with an old logic circuit 1 and extracting the difference between the circuits 1 and 2 as a changing extent. Then an AND gate 12 is obtained by performing fan-out tracing on the circuit 2 from the inverter 17 in corresponding to the extracted changing extent and limiting an influenced part affected by a change. Thereafter, a circuit 5 is obtained by performing fan-in tracing on the circuit 2 from the influenced part and limiting the influencing part which gives an influence to the influenced part, and then, deciding a retesting extent. Since the test patterns required only for the retesting extent 5 are subjected to inputs 15 and 16, a total of four kinds (22=4) of patterns are sufficient.


Inventors:
YAMAGIWA HAJIME
Application Number:
JP24847791A
Publication Date:
March 12, 1993
Filing Date:
September 03, 1991
Export Citation:
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Assignee:
HOKURIKU NIPPON DENKI SOFTWARE
International Classes:
G06F11/22; G06F11/25; G06F11/26; G06F17/50; H03K19/00; G01R31/28; (IPC1-7): G01R31/28; G06F11/22; G06F11/26; G06F15/60; H03K19/00
Attorney, Agent or Firm:
Masaki Yamakawa



 
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