To increase resistance to an error in software in operation with securing high performance and with small scale additional circuit in a logic LSI like a processor, etc.
Respective logic circuits 200, 201, 202, 203 consist of plural stages of logic gates to output signals with positive polarity and negative polarity by every logic gate and a latch 151 separately latches the output signals with positive polarity and negative polarity of the logic circuits. The output signals with positive polarity and negative polarity of each of the last logic circuit stages 200, 201 are made into either positive polarity or negative polarity for each output signal and latched by a latch 152. The output signals with positive polarity and negative polarity of the logic circuits 200 and 201 are inputted in AND gates 161, 162 and NOR gates 171, 172 of positive logic just in front of the latch 152, the output is inputted in OR gates 163, 173 and when either output is indicated to be 'true', the error is found and an instruction is executed again.
MIKI YOSHIO
KAWASHITA TATSUYA
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