Title:
LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JP3396763
Kind Code:
B2
Abstract:
PURPOSE: To provide a logic circuit of a new structure which can be easily produced in a bipolar process and with a high degree of integration and can work at a high speed.
CONSTITUTION: The emitter E0 of a standard NPN transistor TR0 is connected to a bias terminal BIAS together with the base B0 and the collector C0 connected to a voltage source +Vcc and the base B1 of a lateral PNP TR1 respectively. The emitter E1 of the TR1 is connected to a voltage source Vcc together with the base B1 connected to the collector C0 of the TR0 and also to an input terminal IN respectively. The collectros C1, C2, C3... Cn are connected to the output terminals OUT1, OUT2, OUT3... OUTn respectively. The Schottky diodes SBD1, SBD2, SBD3... SBDn are connected between the base B1 and the collectros C1, C2, C3... Cn of the TR1 with the cathodes and the anodes turned toward the base and the collector respectively.
Inventors:
Shigeru Nakagawa
Application Number:
JP15609392A
Publication Date:
April 14, 2003
Filing Date:
May 22, 1992
Export Citation:
Assignee:
Nippon Texas Instruments Co., Ltd.
International Classes:
H01L27/082; H01L21/8222; H01L21/8226; H03K19/013; H03K19/082; H03K19/091; (IPC1-7): H03K19/091; H01L21/8222; H01L21/8226; H01L27/082
Domestic Patent References:
| JP4225273A | ||||
| JP5651856A |
Attorney, Agent or Firm:
Masataka Sasaki