Title:
LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JP3471268
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a logic circuit capable of securing a wide timing margin in control signals even under a high-speed operation and improving operation accuracy.
SOLUTION: The control signals tA, tB, tC and tD successively rise at each half clock of an external clock CLK. Also, the control signal tx rises at the same timing as the control signals tA and tC and the control signal ty rises at the same timing as the control signals tB and tD. Thus, even when the length of one cycle of the control signals tx and ty in an output circuit is turned to be equivalent to one clock of the external clock CLK, parallelly inputted 2-bit data are successively and serially outputted. Thus, the rise and fall of the control signals tx and ty are easily controlled and a wide margin is secured. For instance, when one clock is 10n seconds, the rise and fall of the control signals tx and ty are controlled for every 5n seconds.
Inventors:
Kazunori Maeda
Application Number:
JP35150199A
Publication Date:
December 02, 2003
Filing Date:
December 10, 1999
Export Citation:
Assignee:
NEC
NEC Electronics Corporation
NEC Electronics Corporation
International Classes:
H03K19/20; G11C7/10; H03K21/08; H03M9/00; (IPC1-7): H03K19/20; H03K21/08
Domestic Patent References:
| JP11203863A | ||||
| JP11176158A | ||||
| JP991955A | ||||
| JP2000137982A |
Attorney, Agent or Firm:
Masanori Fujimaki
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