Title:
LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JP3493956
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the fluctuation of the operating characteristic of a DCFL (direct coupling FET logic circuit) without deteriorating the high integrating ability of the DCFL nor changing an already existing process.
SOLUTION: Relating to the DCFL as a circuit the drain electrode 8 and gate electrode 9 of a D-FET 2, the source of the D-FET 2, an electrode 7 which works as the drain of an E-FET 3, and the gate electrode 11 and source electrode 10 of the E-FET 3 are sequentially arranged. Between the source electrode 10 and electrode 7 of the E-FET 3, the active layer 6 of the E-FET 3 is formed in the surface layer section of a GaAs substrate 4. Between the drain electrode 8 of the D-FET 2 and electrode 7, the active layer 5 and source resistor 22 of the D-FET 2 are formed in the surface layer section of the GaAs substrate 4. The active layer 6 of the E-FET 3 and the source resistor 22 of the D-FET 2 are formed in the same structure in the same process.
Inventors:
Takahiro Katamata
Application Number:
JP16332297A
Publication Date:
February 03, 2004
Filing Date:
June 04, 1997
Export Citation:
Assignee:
MURATA MANUFACTURING CO.,LTD.
International Classes:
H03K19/0952; H01L21/8234; H01L27/088; (IPC1-7): H03K19/0952; H01L21/8234; H01L27/088
Domestic Patent References:
| JP5955627A | ||||
| JP63299514A | ||||
| JP61129920A | ||||
| JP59223027A | ||||
| JP2192734A | ||||
| JP1233914A | ||||
| JP2224369A |
Attorney, Agent or Firm:
Masafusa Nakano
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