PURPOSE: To obtain the logic circuit with fast logic output switching speed by providing a level latch means latching the level of 1st and 2nd transistors(TRs) to a prescribed level respectively.

CONSTITUTION: Level latch means(PMOS, NMOS) 5, 6 latch the level of a control electrode of a 2nd TR Q3 to a level lower than the sum of a 1st threshold voltage of a 1st TR Q1 and a 2nd threshold voltage of the 2nd TR Q3 by a slight value when the 1st TR Q1 is turned on. Moreover, the level latch means (PMOS, NMOS) 5, 6 latch the level of the control electrode of the 1st TR Q1 to a level higher than the sum of the 1st threshold voltage of the 1st TR Q1 and the 2nd threshold voltage of the 2nd TR Q3 by a slight small value when the 2nd TR Q2 is turned on. Thus, the switching speed of the logic output is quickened.