Title:
LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JPH0786906
Kind Code:
A
Abstract:
PURPOSE: To protect a circuit from the voltage transition of electrostatic discharge or the like by respectively generating high and low logic signal voltages by the positive feedback connection of two transistors for which a gate is not directly connected to a voltage source line or a ground line. CONSTITUTION: When a voltage is present in the voltage source line 15, a MOSFET 31 is turned on and a high logic signal line 38 connected to the source 33 is pulled up to the voltage level of the voltage source line 15. The MOSFET 35 is turned ON since the gate 36 is connected to the high logic signal line 38 and a low logic signal line 39 connected to the drain 37 is pulled down to the voltage level of the ground line 10. For the MOSFET 31, since the gate 32 is connected to the low logic signal line 39, positive feedback is applied in a direction to be turned on. Thus, the high logic signal voltage and the low logic signal voltage are established. Since the gates of both FETs are not directly connected to the voltage source line or the ground line, faults by a surge voltage intruding from the outside are not received.
Inventors:
MAAKU JIYON RIIDO
JIEI DEIIN MAKUDOGARU
KURISUTEIN MARII KIYASUPAA
JIEI DEIIN MAKUDOGARU
KURISUTEIN MARII KIYASUPAA
Application Number:
JP22574994A
Publication Date:
March 31, 1995
Filing Date:
August 26, 1994
Export Citation:
Assignee:
HEWLETT PACKARD CO
International Classes:
H03K19/0175; H03K3/013; H03K3/356; H03K17/16; H03K17/22; H03K19/003; (IPC1-7): H03K19/003; H03K19/0175
Attorney, Agent or Firm:
Endo Kyo
Next Patent: パターン・データ処理装置