To provide a data latch circuit that is operated by a single phase clock signal without separately providing a single phase/biphase conversion circuit.

A common source transistor(TR) Q5 is connected to a point under a common source of data reception differential pair TRs Q1, Q2 and a common gate TR Q6 is connected to a point under a common source of data reception differential pair TRs Q3, Q4. A source of the common gate TR Q6 is connected to a gate of a common source TR Q5. A gate-source voltage Vgs of the TR Q5 has the same polarity as that of a clock signal CK but the Vgs of the common gate TR Q6 has an opposite polarity to that of the clock signal CK. Thus, the TRs Q5, Q6 are operated complementarily and the single phase clock signal CK selects a data fetch state and a holding state.