PURPOSE: To solve a problem of prolonging processing time even in automatic generation by increasing a combination of test patterns in an exponential man ner.
CONSTITUTION: A test data writing circuit (a) comprises a pullup element 31 and a switching element 35. The pullup element 31 and the switching element 35 are connected to 'high' and 'low' wires or a power source line in an integrated circuit separately. Hereafter, the 'high' and 'low' wires (or the power source line) in the integrated circuit are indicated by - and inverse delta marks individually. Here, when a writing signal is sent from a selection switch 10, the switching element 35 is turned ON to perform a writing of low data into a test node W. This circuitry is used in the writing of the low data.
| WO/2020/144478 | DETECTION OF PULSE WIDTH TAMPERING OF SIGNALS |
| JPH02210281 | LSI TESTING METHOD |
| WO/1996/030775 | PROCESS AND CIRCUIT FOR MONITORING A DATA PROCESSING CIRCUIT |
FUDA AKIRA
MIWA MASAHIKO
