To reduce the memory capacity required for storing data.

This apparatus is provided with an m-bit counter 15 for repeatedly performing the counting synchronously with a system clock, a capture pulse generator 13 to detect a change point each time a logic signal is changed, after counting by the counter 15 has started for starting the storage of logic signals, a capture unit 16 for outputting the count value of the counter 15 and a level value of the logic signal, when the change point of the logic signal is detected, a comparator 17 to determine that the counter 15 counted for one round without having next change after the change point of the level value of the logic signal, an OR gate 25 for outputting a write trigger signal WT when the change point of the logic signal is detected, and when it is determined that the counter counted for one round, and an FIFO unit for writing the count value and the level value from the capture unit 16 by the write trigger signal (WT).