To provide a logic simulation device capable of easily executing a skew check between pins at a high speed.

A timing verification device 1 selects a logic element of a skew check target directly connected to an external I/O pin or indirectly connected to an external I/O pin through a logic element out of the skew check target (e.g. a logic circuit such as an inverter, a NAND, a NOR or the like) on the basis of connection information about logic circuits of an LSI and a logic circuit information 12 defining timing check values to logic elements, and updates only the timing check value of the selected logic element.