PURPOSE: To provide a logic synthesization and layout arrangement wiring device for shortening the length of connecting wiring from a power source/ ground cell to a logic cell.

CONSTITUTION: This device is provided with a net list input part 5, layout cell arrangement condition setting part 3, connection existence probability extracting part 6 for calculating probability for the logic cell connected to the power source/ground cell to exist in an area to arrange an unadjacent logic cell, addition probability judging part 7 for judging the addition of the power source/-ground cell when the calculated probability is higher than a specified value, and adding part 8 for adding the power source/ground cell. Thus, degradation in the characteristics of a semiconductor can be minimized.