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Patent Searching and Data


Title:
LOGIC SYNTHESIZER
Document Type and Number:
Japanese Patent JPH06139305
Kind Code:
A
Abstract:

PURPOSE: To generate not only an internal logic circuit in an LSI but also a buffer cell for connection to the outside at the time of circuit design of the LSI to improve the design efficiency and to generate the LSI having optimum characteristics.

CONSTITUTION: After a network list of the internal logic circuit of the LSI is generated, interface specifications of external interface pins for interface between the LSI and the output which are inputted by a specification input part u1 are described by an LSI external interface specification description part u2. A buffer cell adapted to these specifications is selected by an interface buffer determining part u3 and is inserted between the internal logic circuit in the network list and the external interface pins by a buffer inserting part u4. Thereafter, the circuit is so adjusted by an adjustment part u6 that delay, design rules, and the power consumption inputted by a designer are satisfied.


Inventors:
KOMOTA MICHIO
MIYAMOTO NORIKO
Application Number:
JP28902192A
Publication Date:
May 20, 1994
Filing Date:
October 27, 1992
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F17/50; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Soga Doteru (6 people outside)