Title:
メモリ制御回路の論理検証装置及び方法
Document Type and Number:
Japanese Patent JP4475621
Kind Code:
B2
Abstract:
A CPU model issues a memory access request to a memory control circuit by executing a verification test program. A transaction monitor monitors a transaction generated on a system bus, and detects and holds a transaction of memory access from the CPU model. A memory model responds to access from the memory control circuit, and acquires transaction information of that access. A memory access checker logically verifies the memory control circuit using the transaction information acquired by the memory model, and the transaction information held by the transaction monitor.
Inventors:
Hiroshi Hosokawa
Application Number:
JP2001119971A
Publication Date:
June 09, 2010
Filing Date:
April 18, 2001
Export Citation:
Assignee:
Canon Inc
International Classes:
G01R31/28; G11C29/02; G06F17/50
Domestic Patent References:
| JP10283388A |
Attorney, Agent or Firm:
Yasunori Otsuka
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura