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Patent Searching and Data


Title:
LOGICAL CHECK OF PRINTED CIRCUIT BOARD UNIT
Document Type and Number:
Japanese Patent JPS63233384
Kind Code:
A
Abstract:

PURPOSE: To improve reliability by inputting a control signal from output inhibiting means to a logical circuit with an unknown logic in mounted logical circuits to inhibit the logical circuit from generating an output and testing the other logical circuits in a test.

CONSTITUTION: When a printed circuit board unit 1 to which a plurality of logical circuits are mounted is tested, by inputting a test/actual operation change over signal to a logical circuit 21-2 with an unknown circuit structure, for example, such as the LSI of an MPU, the output of the circuit 21-1 is inhibited. At this time, a test pattern is inputted to a logical circuit 21-1 with a circuit structure known in advance and the circuit 21-1 is tested at first. An output signal (a) from the circuit 21-1 is used an input signal to the logical circuits to be subject to a test to be performed later. The signal (a) skips over the circuit 21-2 by short-circuiting it by a switch 23 via probes 22 and the signal (a) is made an input signal (b) to another logical circuit 21-3 with a known circuit structure whereby the circuit 21-3 is tested next. The output signal (c) of the circuit 21-3 is made the output pattern of the unit 1 and compared 24 with an expected value to judge defective or normal.


Inventors:
TANAKA HAJIME
SAWADA AKIO
Application Number:
JP6609287A
Publication Date:
September 29, 1988
Filing Date:
March 20, 1987
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G01R31/28; G01R31/317; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Sadaichi Igita