LOGICAL CIRCUIT HAVING COMPLEMENTARY OUTPUT

Title:

LOGICAL CIRCUIT HAVING COMPLEMENTARY OUTPUT

Document Type and Number:

Japanese Patent JPS581328

Kind Code:

A

Abstract:

PURPOSE: To shorten the time difference between two outputs of a logical circuit which has complementary outputs, by arranging output transistors (TR) at the emitter and collector of an input TR.

CONSTITUTION: Although the output of a TTL circuit is inputted to an inverter heretofore to obtain complementary outputs, the 2nd npn output TRT3 is connected to even the collector of an inout pnp TR in this invented circuit. Then, the output signals are lead out of the collectors of the TRs T2 and T3. Consequently, the outputs O1 and O2 are the complementary outputs and the time difference between the outputs are very less.

Inventors:

SHIMAUCHI YUKI
YASUDA YASUSHI
MITONO KATSUHARU
ENOMOTO HIROSHI
TAWARA AKINORI

Application Number:

JP9837581A

Publication Date:

January 06, 1983

Filing Date:

June 26, 1981

Export Citation:

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Assignee:

FUJITSU LTD

International Classes:

H03K19/082; H03K5/151; (IPC1-7): H03K19/082

Attorney, Agent or Firm:

Aoki Akira

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