PURPOSE: To obtain a logic LSI possible for high speed operation by giving a reference signal to plural non-threshold logic circuits provided adjacently and extracting a complementary signal of an inverse function respectively from an OR output side and a NOR output side so as to decrease the skew of the signal.
CONSTITUTION: An element comprising transistors (TR)Q1, Q2 and resistors R1∼ R3 constituting a non-threshold logic circuit NTL is formed in a rectangular unit cell region CC, the four regions CC are arranged symmetrically so as to constitute an internal logic circuit of the logic LSI. An emitter coupled logic circuit ECL is constituted by the basic circuit and a reference clock CK0 is inputted to input TRs Q11∼Q13. Furthermore, a clock CK is extracted from an emitter follower EF1 comprising a TRQ21 of an OR side and a clock CN is extracted from an FF2 comprising a TRQ22 of a NOR side. The complementary signal of opposite phase is extracted, the skew of the signal is reduced and the high speed operation of the circuit is attained.
ISHII SHIYUUICHI
USAMI MITSUO
| JPS4915916A | 1974-02-12 |