Title:
LOGICAL OPERATION UNIT
Document Type and Number:
Japanese Patent JP3533825
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To remove non-flexibility, the low speed of function change and a large amount of clock consumption by executing an inter-bit operation with arbitrary combination from inputted n-bit data and output it to one plural arbitrary bit positions among m-bits.
SOLUTION: An eight bit input/eight bit outputs function circuit FC1 is a logical operation unit and it has the input side masking circuit IM of n-bits, the logical operation execution part AE of n-bit inputs/m-bit outputs at maximum, the output side masking circuit OM of m-bits and a data output port 13. Then, the inter-bit operation of arbitrary combination is executed from inputted n-bit data and it is outputted to one or plural arbitrary bit positions among m-bits. The logical operation execution part AE executes the logical operation of n-bit inputs/m/bit outputs at maximum, which executes the inter-bit logical operation with only bit data which is set to be valid in the input side masking circuit IM as an operation object.
Inventors:
Ishii, Kenji
Tsutsui, Akihiro
Miyazaki, Toshiaki
Tsutsui, Akihiro
Miyazaki, Toshiaki
Application Number:
JP13085596A
Publication Date:
May 31, 2004
Filing Date:
April 26, 1996
Export Citation:
Assignee:
NIPPON TELEGR & TELEPH CORP <NTT>
International Classes:
G06F7/00; G06F7/76; G06F9/305; (IPC1-7): G06F9/305; G06F7/00
Attorney, Agent or Firm:
川久保 新一