Title:
LOGICAL PROCESSING CIRCUIT, SEMICONDUCTOR DEVICE, AND LOGICAL PROCESSOR
Document Type and Number:
Japanese Patent JP3900126
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce off-leakage current in an operation mode in which a circuit actually operates.
SOLUTION: The logical processing circuit is constituted so that, for example, data held by flip-flops 11 to 13 at the time of rising of a clock signal CK is processed by a logical gate circuit network 31 to which power is supplied during a low level state period of the clock signal CK and its processing result is held in flip-flops 21 to 23 at a state that the power is always supplied to the flip-flops 11 to 13, 21 to 23 at each of front and rear stages. When power supply time to the logical gate circuit network 31 is set to be required minimum, the off-leakage current at the logical gate circuit network 31 is suppressed.
Inventors:
Ichiro Kumada
Application Number:
JP2003294579A
Publication Date:
April 04, 2007
Filing Date:
August 18, 2003
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H01L27/04; H03K19/096; G06F9/38; H01L21/822; H01L21/8238; H01L27/092; H03K3/037; H03K19/00; H03K19/0948; (IPC1-7): H03K19/096; H01L21/822; H01L27/04; H03K3/037
Domestic Patent References:
| JP8065139A | ||||
| JP9200026A | ||||
| JP8509084A | ||||
| JP6224703A | ||||
| JP58006592A |
Attorney, Agent or Firm:
Yoshitsuno Kakuda
Hironobu Isoyama
Hironobu Isoyama
Previous Patent: LIQUID COMPOSITION, METHOD AND DEVICE FOR FORMING FILM, ELECTRO-OPTICAL DEVICE AND ITS MANUFACTURING...
Next Patent: HAIR CARE DEVICE
Next Patent: HAIR CARE DEVICE