Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
LOGICAL SIMULATION DEVICE
Document Type and Number:
Japanese Patent JPS607531
Kind Code:
A
Abstract:

PURPOSE: To obtain a high-speed logical simulation device by using a pipeline operator having a variable logical function, a high-speed register, etc. to attain a pipeline system variable logical operator and to use exclusive hardware.

CONSTITUTION: A pipeline arithmetic device having a variable logical function is provided together with a high-speed register, a main memory and a controller. For instance, the logical data which describes a model to be simulated, the input data to be given to the model and the simulation result are stored in a memory 1. Then the editing processes including the loading, storage, the alteration of data array, etc. are carried out between the memory 1 and a high-speed register 2 in response to a simulation program of a controller 6 and via the load/store/ editing pipelines 3-1 and 3-2. A variable function logical arithmetic pipeline 4 calculates the function code, etc. given from the register 2 and supplies it again to the register 2. Then an editing pipeline 5 supplies the result of calculation again to the pipeline 4 for the next calculation.


Inventors:
MIURA KENICHI
Application Number:
JP11487883A
Publication Date:
January 16, 1985
Filing Date:
June 25, 1983
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
G06F9/38; G06F7/00; G06F17/50; G06F19/00; (IPC1-7): G06F7/00; G06F9/38; G06F15/20
Domestic Patent References:
JPS5814257A1983-01-27
JPS57101938A1982-06-24
JPS58106636A1983-06-25
JPS5619152A1981-02-23
Attorney, Agent or Firm:
Fumihiro Hasegawa



 
Next Patent: CHARACTER PROCESSOR