Title:
LOGICAL TIME CONTROL SYSTEM BY DICENTRALIZED CONTROL
Document Type and Number:
Japanese Patent JPS61272862
Kind Code:
A
Abstract:
PURPOSE:To prevent the turbulence of the time control due to the load fluctuation by making the logical time of own processor equal to the updated message logical time on the basis of an updated message transmitted by a processor updating the logical time of its own processor is smaller. CONSTITUTION:A reception message is read from a reception buffer 320, and is checked to be the logical time updated message outputted from other processors according to the content code. When it is not the updated message, it is connected to an input buffer 370 as it is. When it is the updated message, a logical time (t) set to the real data part of the logical time updated message is compared with a logical time T stored in a logical time memory unit 340. Where T<(t), the logical time T is updated to the (t), which is stored in the logical time memory unit. Then the message is taken out of an output buffer 380, updated to the logical time registered on a table in a logical time control unit 350, and connected to a reception buffer 330.
Inventors:
KOIZUMI MINORU
MORI KINJI
MORI KINJI
Application Number:
JP11405385A
Publication Date:
December 03, 1986
Filing Date:
May 29, 1985
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F1/14; G06F15/16; (IPC1-7): G06F15/16; H04L11/02
Attorney, Agent or Firm:
Katsuo Ogawa