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Patent Searching and Data


Title:
LOGICAL VARIABLE PLA
Document Type and Number:
Japanese Patent JPH01276822
Kind Code:
A
Abstract:

PURPOSE: To attain the combination of many product terms in a narrow chip area by connecting a switch between the output terminal of an AND plane and the input terminal of an OR plane, connecting the output of a control device to the control input of a switch and inputting a control signal.

CONSTITUTION: In a PLA composed of an AND plane 1 and an OR plane 2, plural outputs of the AND plane 1 are respectively connected to the input of plural switches 4, the output of plural switches 4 is connected to plural inputs of the OR plane 2 and the control input terminal of plural switches 4 is connected to a switching control device 3 of the switches 4. The control device 3 is composed of a selector to execute the switching control of a left side part AND plane 1a and a right side part AND plane 1b of the AND plane 1 with the switches 4. Thus, once after the logic is written into the AND plane and the OR plane, the combination of many product terms can be realized by a small area.


Inventors:
KOIZUMI YUJI
Application Number:
JP10703088A
Publication Date:
November 07, 1989
Filing Date:
April 27, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/82; H03K19/177; (IPC1-7): H01L21/82; H03K19/177
Domestic Patent References:
JPS5678233A1981-06-27
JPS57203335A1982-12-13
JPS5523679A1980-02-20
Attorney, Agent or Firm:
Naoki Kyomoto (3 outside)