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Title:
LOOP BACK TEST METHOD
Document Type and Number:
Japanese Patent JPH01303837
Kind Code:
A
Abstract:

PURPOSE: To make inexpensive the constitution for a loop lock test, and to point out an abnormal part in a simple constitution by making the logical sum of the output of drivers in an arbitrary number into the input of a single receiver.

CONSTITUTION: In communicating equipment 4 having receivers 2-1 to 2-m in a smaller number than that of drivers 1-1 to 1-n, a loop back test connector 6 is mounted on a line connector 3, and the loop back test is executed. The loop back connector 6 has the constitution to logical-sum-connect the drivers 1-1 to 1-n in the arbitrary number as a set to one of the respective receivers 2-1 to 2-m by means of a diode 5, and a test process to detect whether or not a signal in an OFF-condition is inputted to the receivers 2-1 to 2-m belonging to the set when the signal which makes the all drivers 1-1 to 1-n in the arbitrary number into the OFF-condition is inputted, and the test process to detect whether or not the input of the signal in an ON-condition is inputted to the receivers 2-1 to 2-m belonging to the set by inputting the signal to successively make the drivers 1-1 to 1-n to the ON-condition are executed. From this, the loop back test including the all drivers and the all receivers can be continuously executed, and the simple abnormal part can be discriminated.


Inventors:
SHIRAI NOBUO
Application Number:
JP13258888A
Publication Date:
December 07, 1989
Filing Date:
June 01, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L25/02; H04L13/00; H04L69/40; (IPC1-7): H04L13/00; H04L25/02
Attorney, Agent or Firm:
Shoji Kashiwaya (1 person outside)



 
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