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Title:
LOOP COUNTING SYSTEM
Document Type and Number:
Japanese Patent JPS5875928
Kind Code:
A
Abstract:

PURPOSE: To use bits other than a prescribed number of high-order digit bits of a register including the most significant digit bit for another purpose, by selecting said high-order digit bits including the most significant digit bit in accordance with the number of loops, and adding or subtracting a value corresponding to the least significant digit bit among the selected bits to or from the storage contents of the register.

CONSTITUTION: When the number of loops is four, the most significant digit bit and succeeding bit C7 and C6 of a counter 2 are used, so the bits C7 and C6 are initialized. In an addition (subtraction) data memory, 01000000 is set. Once a count signal Sc is outputted from a CPU1, an adder-subtracter 5 performs addition (subtraction) between the contents of the counter 2 and those of the data memory 4, and the result is set in the counter 2 again. Said operation is repeated until a zero flag 6 is set. Therefore, other bits of the counter 2 are not under the influence of the counting operation, so those other bits are utilized effectively for another purpose.


Inventors:
YOSHIDA HIDEO
IIZUKA TAIJI
Application Number:
JP17510681A
Publication Date:
May 07, 1983
Filing Date:
October 30, 1981
Export Citation:
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Assignee:
SHARP KK
International Classes:
H03K27/00; (IPC1-7): H03K27/00
Domestic Patent References:
JPS4895170A1973-12-06
JPS5013073A1975-02-10
JP53097961B
Attorney, Agent or Firm:
Sugiyama Takeshi



 
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