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Patent Searching and Data


Title:
LOW FREQUENCY DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPH04219014
Kind Code:
A
Abstract:

PURPOSE: To obtain a delay clock with a waveform having no disturbance and with a desired duty ratio by delaying an input clock by a desired time through the operation in a short time.

CONSTITUTION: The low frequency delay circuit giving an optional delay to an inputted clock and outputting the delayed signal consists of a delay generating means comprising a 1st monostable multivibrator 14 outputting a lock whose pulse width depends on a time constant upon the receipt of the clock, a 1st capacitor being one factor of the time constant and a 1st variable resistor means 15 varying the said time constant by varying its resistance, and of a duty ratio correction means comprising a 2nd monostable multivibrator 19 receiving a delay clock whose pulse width depends on a time constant upon the receipt of the clock from the said 1st monostable multivibrator, a 2nd capacitor being one factor of the said time constant and a 2nd variable resistor 20 means varying the said time constant by varying its resistance.


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Inventors:
SASAKI HIROSHI
Application Number:
JP41010190A
Publication Date:
August 10, 1992
Filing Date:
December 13, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03K5/13; (IPC1-7): H03K5/13
Attorney, Agent or Firm:
Akira Matsumoto