Title:
LOW GLITCH-NOISE DAC
Document Type and Number:
Japanese Patent JP2017103783
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To control glitch noise in a low-power, high-resolution, wideband DAC.SOLUTION: An N-bit digital-to-analog converter (DAC) includes N input stages each of which generates the same amount of current and includes a pair of similarly sized transistor switches responsive to differential bits. The 2-1 input stages associated with the M most significant bits of the DAC are connected in parallel and deliver the currents of the input stages differentially to the DAC's current summing nodes. Each of the remaining (N-M) stages includes a resistive network that supplies a current defined by a binary weight of the stage's bit position within the DAC. The (N-M) stages deliver the currents of the stages differentially to the current summing nodes. The DAC further includes an impedance attenuator adapted to maintain the impedance of the current summing nodes and the voltage difference between the current summing nodes within a range defined by a gain of a differential amplifier disposed in the impedance attenuator.SELECTED DRAWING: Figure 12
Inventors:
DONWHANG THEO
LEE SANG MIN
LEE SANG MIN
Application Number:
JP2016251363A
Publication Date:
June 08, 2017
Filing Date:
December 26, 2016
Export Citation:
Assignee:
QUALCOMM INC
International Classes:
H03M1/68
Domestic Patent References:
| JPH10112654A | 1998-04-28 | |||
| JPH07162240A | 1995-06-23 | |||
| JP2012050004A | 2012-03-08 | |||
| JP2013507066A | 2013-02-28 |
Foreign References:
| US20030001766A1 | 2003-01-02 | |||
| US20100213983A1 | 2010-08-26 | |||
| US20020030619A1 | 2002-03-14 | |||
| US20060092065A1 | 2006-05-04 |
Other References:
黒田 忠広 監訳, アナログＣＭＯＳ集積回路の設計 応用編, JPN6018046344, 30 March 2003 (2003-03-30), JP, pages 375 - 380, ISSN: 0003926763
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada