PURPOSE: To reduce periodic noise due to the operation of the circuit by providing a common clock having a prescribed period to each shift register to synchronize the operation of each shift register with the clock.

CONSTITUTION: The outputs Q of flip-flops 10d, 11d, 12d, at the final stage are supplied respectively to the input T of flip-flops 10a, 11a, 12a of the first stage. Moreover, processing of ORs 13, 14 between the output Q of flip-flops 10c, 11c at the 3rd stage of Johnson counters 7, 8 and the output Q of the flip- flops 10d, 11d at the final stage is outputted as carry signals RCO1, RCO2. Thus, the basic clock CLK is supplied to the timing input T of the flip-flops 10a-10d of the Johnson counter 7 via a buffer to obtain the equal delay with that of a logic gate in order to make matching with the operation of other Johnson counters 8, 9. Thus, power noise due to the operation of the counter circuits is reduced.