Title:
LOW-POWER CMOS CIRCUIT
Document Type and Number:
Japanese Patent JP3107545
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a low-power CMOS circuit whose power consumption in the standby mode is minimized.
SOLUTION: A 1st PMOS transistor(TR) PM1 and a 1st NMOS TR NM1 are connected in series between a terminal of a power supply voltage VDD and a terminal of a ground voltage VSS in a CMOS inverter circuit. Here, the 1st PMOS TR PM1 and the 1st NMOS TR NM1 are configured so that they have a low threshold voltage and a high gamma factor (γ), when each of their wells receives a reverse bias voltage Vbs. The 1st PMOS TR PM1 and the 1st NMOS TR NM1 are configured in such a way that the 1st PMOS TR PM1 and the 1st NMOS TR NM1 connected to the ground voltage VSS terminal have a high gamma factor, when they receive the back bias voltage Vbs in the standby mode.
Inventors:
Candecan
Application Number:
JP97299A
Publication Date:
November 13, 2000
Filing Date:
January 06, 1999
Export Citation:
Assignee:
ELGE SEMICON Company Limited
International Classes:
H03K17/16; H01L27/085; H03K17/687; H03K19/00; H03K19/0948; H03K19/096; (IPC1-7): H03K19/0948; H03K17/16; H03K17/687; H03K19/096
Domestic Patent References:
| JP5108194A | ||||
| JP9162417A |
Attorney, Agent or Firm:
Hironobu Onda