Title:
低電力高性能記憶回路及び関連方法
Document Type and Number:
Japanese Patent JP4409958
Kind Code:
B2
Abstract:
An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.
Inventors:
Kang, San-mo
Yo, Sun-Moon
Yo, Sun-Moon
Application Number:
JP2003581203A
Publication Date:
February 03, 2010
Filing Date:
March 27, 2003
Export Citation:
Assignee:
The Regents of The University of California
International Classes:
G11C11/412; G11C11/41; H03K3/012; H03K3/356; H03K3/3565; H03K17/00; H03K17/04; H03K17/06; H03K17/687; H03K19/00; H03K19/0175
Domestic Patent References:
| JP10172278A | ||||
| JP2094196A | ||||
| JP2003188696A | ||||
| JP54072640A |
Attorney, Agent or Firm:
Atsushi Aoki
Jun Tsuruta
Tetsuro Shimada
Shimichi Akihisa
Masaya Nishiyama
Jun Tsuruta
Tetsuro Shimada
Shimichi Akihisa
Masaya Nishiyama