Title:
LOW POWER INTEGRATED C-MOS CIRCUIT
Document Type and Number:
Japanese Patent JPS58112361
Kind Code:
A
Abstract:
The control power input of a power stage designed in the form of a CMOS inverter can be considerably reduced according to the invention in that, with the aid of a driver stage splitting the digital input signal, each of the two gate electrodes of the two field-effect transistors of the power stage, are simultaneously but separately controlled by each time one driver signal of the same polarity, thus each time raising the source-gate voltage of one of the two field-effect transistors above its threshold voltage value.
Inventors:
FURITSUTSU GIYUNTAA ADAMU
Application Number:
JP22035982A
Publication Date:
July 04, 1983
Filing Date:
December 17, 1982
Export Citation:
Assignee:
ITT
International Classes:
H01L21/8238; H01L27/092; H03K19/0185; H03K19/0948; (IPC1-7): H01L27/08; H03K19/094
Attorney, Agent or Firm:
Takehiko Suzue