Title:
Low threshold voltage antifuse device
Document Type and Number:
Japanese Patent JP5947361
Kind Code:
B2
Abstract:
A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits. The threshold voltage of the anti-fuse device is lowered by omitting some or all of the threshold adjustment implants that is used for high voltage transistors fabricated in the I/O circuits.
Inventors:
Kurjano Wicks, Rodeck
Application Number:
JP2014238642A
Publication Date:
July 06, 2016
Filing Date:
November 26, 2014
Export Citation:
Assignee:
SIDENSE CORP.
International Classes:
H01L27/10
Domestic Patent References:
| JP2011517067A | ||||
| JP2001196470A | ||||
| JP2010529685A | ||||
| JP4323867A | ||||
| JP2007536744A |
Foreign References:
| US20060292754 | ||||
| US20070257331 | ||||
| WO2009121182A1 | ||||
| US20090250726 | ||||
| WO2008151429A1 |
Attorney, Agent or Firm:
Yoshiyuki Inaba
Toshifumi Onuki
Toshifumi Onuki