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Title:
LRU DEVICE
Document Type and Number:
Japanese Patent JPS6381549
Kind Code:
A
Abstract:

PURPOSE: To attain an LRU device with a high bit rate by providing a detection means storing the least class data among N sets of storage elements to be addressed and outputting the address of the storage element.

CONSTITUTION: In the LRU (Least Recently Used) algorithm, a storage element storing the least class data among N sets of addressed storage elements is detected without using a reference bit and an output data representing the address of the storage element is outputted by the detection means. Thus, an input data DIN corresponding to the page frame number accessed this time is inputted to the LRU device to obtain an output data DOUT corresponding to the page frame number accessed in the far past, in the page frame in the main memory, for example. Thus, the LRU device executing the true LRU algorithm is obtained, and the hit rate of a computer or the like having fast operating speed and various virtual storage management device is improved rapidly.


Inventors:
UYA MASARU
Application Number:
JP22669486A
Publication Date:
April 12, 1988
Filing Date:
September 25, 1986
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F12/12; (IPC1-7): G06F12/12
Domestic Patent References:
JPS5017542A1975-02-24
Attorney, Agent or Firm:
Tomoyuki Takimoto