PURPOSE: To reduce an additional circuit for facilitating a test by providing a gate which ANDs an OR of signals inputted to logic circuits in an LSI and a gate which ORs output signals of both gates exclusively.

CONSTITUTION: In an LSI circuit 1B, an output FF 1B-7 having a scan path fetches the output signal of an in-LSI logic circuit 1B-1 and the fetched value is scanned out. Further, an output selector circuit 1B-8 output the output signal of the FF 1B-7 or the output of the circuit 1B-1 to an output terminal 1B-10. Further, an OR gage 1B-3 ORs all signals inputted to an input terminal 1B-2 and an AND gate 1B-4 ANDs all input signals; when an XOR gate 1B-5 ORs the output signals of the gates 1B-3 and 1B-4 exclusively and an input FF 1B-6 having a scan path fetches the output signal of the gate 1B-5, its value is scanned out.