Title:
LSI FUNCTION DESIGN SUPPORT DEVICE
Document Type and Number:
Japanese Patent JP3725230
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To generate hardware description data which corresponds to various targets and which can be logically synthesized with high quality from extension state transition drawing data.
SOLUTION: Hardware description data by HDL(hardware description language) is generated from extension state transition drawing data by permitting CPU to execute following operation based on a program stored in a memory. Description data by HDL of a part operating as a finite state machine is generated (S22) based on inputted extension state transition drawing data. Then, description data by HDL of a data path part is generated (S24). Data are outputted as hardware description data in a reregister transfer level being a design object (S28). Thus, hardware description data of LSI, in which an FSM part and the data path part are constituted as different blocks, can be obtained. Consequently, the logic synthesis tool of a high compression rate can be used on the FSM (finite state machine block) part and debugging after logic synthesis becomes easy.
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Inventors:
Takamitsu Yamada
Kazunobu Sugaya
Yoshiharu Oka
Kazunobu Sugaya
Yoshiharu Oka
Application Number:
JP4320496A
Publication Date:
December 07, 2005
Filing Date:
February 29, 1996
Export Citation:
Assignee:
株式会社リコー
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP8147338A | ||||
| JP8050603A |
Attorney, Agent or Firm:
Aoyama Aoi
Osamu Kawamiya
Osamu Kawamiya