To attain logical designing and automatic generation of diagnosis data without considering the impossibility of failure detection due to logical scale and step number by detecting the failure of a partial circuit through a diagnosis easing circuit according to signals for only diagnosis.
When a value is set to an input FF group 1, it is propagated to a combination circuit 2, and is arrives at a select circuit 7 of a diagnosis part 14 through a signal route 19 for only diagnosis from a gate output part 18. At this time, the internal signal of a logical part 13 is selected according to a select control signal 9, and the signal propagation result of the circuit 2 is propagated to a scanning circuit group 8 for diagnosis. Next, the value propagated to the circuit group 8 is picked up from an out-edge pin 11 by sending control signal A15 and B16. Thus, the signal propagation result of the circuit 2 is observed by using the pin 11 so as to complete testing of the circuit 2. Therefore, any failure of a defective part 17 in the circuit 2 can be detected without using an output FF group.
Next Patent: TESTING METHOD AND TESTING CIRCUIT OF LOGIC CIRCUIT