Title:
【発明の名称】検査容易化設計方法
Document Type and Number:
Japanese Patent JP3117676
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make it possible to guarantee a high fault detection rate in RTL, by deciding a resister to be scan-converted from the registers in an RTL circuit to make the circuit structure to be a designated circuit structure easy to be inspected. SOLUTION: The circuit structure easy to be inspected is designated (step 11). A digraph is generated from RTL design data concerning the RTL circuit being an integrated circuit which is designed in RTL (step 12). When the circuit structure of the RTL circuit at the time of inspecting regards the normal data input of the register to be a scan register as a pseudo-external output and a data output as a pseudo-external input, the register (the one to be scan- converted) to be replaced with a scan register in the generated digraph is decided in order to obtained designated circuit structure (step 13). Thus, the register to be a scan register is decided so that the high fault detection rate is guaranteed in an upstream design stage.
Inventors:
Toshinori Hosokawa
Tomoo Inoue
Hideo Fujiwara
Tomoo Inoue
Hideo Fujiwara
Application Number:
JP743198A
Publication Date:
December 18, 2000
Filing Date:
January 19, 1998
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F17/50; G01R31/28; (IPC1-7): G06F17/50; G01R31/28
Domestic Patent References:
| JP765064A |
Other References:
【文献】3.本原章、外4名、“レジスタ転送レベルでのテスト容易化設計手法”情報処理学会シンポジウム論文集 DAシンポジウム’94、情報処理学会、1994年8月、Vol.94、No.5、P.89~94
【文献】4.細川利典、外3名“RTL回路分割を用いたテスト容易化設計手法”、情報処理学会シンポジウム論文集DAシンポジウム’96、情報処理学会、1996年8月、Vol.96,No4、P.225~230
【文献】5.細川俊典、外3名”n重整列構造に基づくパーシャルスキャン設計方法”、情報処理学会シンポジウム論文集DAシンポジウム’97、情報処理学会、1997年7月、Vol.97、No4、P.51~56
【文献】4.細川利典、外3名“RTL回路分割を用いたテスト容易化設計手法”、情報処理学会シンポジウム論文集DAシンポジウム’96、情報処理学会、1996年8月、Vol.96,No4、P.225~230
【文献】5.細川俊典、外3名”n重整列構造に基づくパーシャルスキャン設計方法”、情報処理学会シンポジウム論文集DAシンポジウム’97、情報処理学会、1997年7月、Vol.97、No4、P.51~56
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)