Title:
MCUのパワーノイズ防止回路
Document Type and Number:
Japanese Patent JP4384745
Kind Code:
B2
Abstract:
052450152 A power noise preventing circuit for a microcontroller unit (MCU) is provided that prevents an erroneous operation of the MCU caused by power supply noise. The power noise preventing circuit for the MCU can include a power fail detecting circuit that controls a power fail signal by comparing supplied power to a preset fail voltage of a MCU and a system clock generating circuit that receives a clock signal and generates a first system clock signal that determines a state of a system. A clock freezing and synchronizing circuit fixedly outputs a second system clock signal at a state of the first system clock signal when the power falls below the preset fail voltage and the power fail signal is enabled. The clock freezing and synchronizing circuit further outputs the second system clock signal synchronized with the first system clock signal when the power fail signal is disabled.
Inventors:
Hyun Hyun Kim
Application Number:
JP1073099A
Publication Date:
December 16, 2009
Filing Date:
January 19, 1999
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
G06F1/04; G06F11/07
Domestic Patent References:
| JP8032026A | ||||
| JP9054727A | ||||
| JP5303443A | ||||
| JP4070912A | ||||
| JP8044452A |
Attorney, Agent or Firm:
Tomijio Sasashima